1. Field of the Invention
The invention relates to a circuit, and more particularly to a built-in self test (BIST) circuit for testing not only the differential non-linearity(DNL) error and the integral non-linearity(INL) error of an analog-to-digital converter(ADC) but also the period jitters of a clock signal. The clock signal can be outputs of an oscillator or a phase lock loop.
2. Description of the Related Art
A phase lock loop (PLL) is widely used in frequency synthesization, clock correction, clock distribution and phase demodulation. Frequency synthesization, clock correction, clock distribution and phase demodulation are generally used in optical fiber links, radio phones and computers. Clock variations such as period jitters of the phase lock loop circuit may degrade performance and limit applications of the phase lock loop circuit. Thus, for high-speed applications, precise and cost effective measurement on clock variation and period jitter is required.
FIG. 1A is a block diagram showing a conventional BIST for measuring period jitters as disclosed in U.S. Pat. No. 6,937,106. A conventional BIST circuit uses time-to-digital converter 2 to measure period jitters and divided by n (1/n) 1 prior to time-to-digital converter 2 is used to enlarge the period jitters of a signal under test to enhance test precision. FIG. 1B is a detailed schematic view showing a conventional time-to-digital converter 2. The test resolution of the circuit shown in FIG. 1A is limited by the delay of the component in FIG. 1B. Thus, the resolution of the signal under test that is not divided by 1/n divider 1 is within limits.
FIG. 2 is a block diagram showing another conventional BIST circuit 20 for measuring period jitters comprising control signal generator 21, period to voltage converter 22 and ADC 23. Two output signals Q1 and Q2 are generated by control signal generator 21 according to a test signal T to control the charge time of comparator 26 from period to voltage 22. Charge pump 25 converts the charge time to voltage and stores the voltage in capacitor 24. Then, ADC 23 converts the load voltages to digital value. Output value of BIST 20 depends on resolution of ADC 23.
High precision period jitter of PLL is measured through the combination of BIST circuit 20 shown in FIG. 2 and high resolution ADC 23. Note that a defective ADC 23 may cause errors when measuring. Typically, using the ADC of current technologies is very difficult to detect the jitter less than 10 ps under the period of 1 ns˜100 ns.